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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
FEATURES
* Two differential LVPECL outputs * One differential LVPECL clock input * IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Output frequency: 2GHz (typical) * Output skew: <15ps (typical) * Part-to-part skew: TBD * Additive phase jitter, RMS: TBD * Propagation delay: 350ps (typical) * Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V * -40C to 85C ambient operating temperature * Availabe in both standard and lead-free RoHS compliant packages
GENERAL DESCRIPTION
The ICS858012 is a high speed 1-to-2 Differentialto-2.5V, 3.3V LVPECL Fanout Buffer and is a HiPerClockSTM member of the HiPerClockSTM family of high performance clock solutions from ICS. The ICS858012 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVPECL, LVDS, LVHSTL and HCSL to be easily interfaced to the input with minimal use of external components. The ICS858012 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.
IC S
BLOCK DIAGRAM
PIN ASSIGNMENT
VCC
IN 1 VT 2 Q0 nQ0 VREF_AC 3 nIN 4
16 15 14 13 12 11 10 9 5
VCC
VCC
VEE
VEE
Q0 nQ0 nQ1 Q1
VEE
VEE
Q1 nQ1 VREF_AC
ICS858012
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
858012AK
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1
VCC
IN VT nIN
6
7
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
Type Input Input Output Input Power Power Output Output Description Non-inver ting LVPECL differential clock input. Termination input. Reference voltage for AC-coupled applications. VREF_AC = to VCC - 1.38V. Inver ting differential LVPECL clock input. Positive supply pins. Negative supply pin. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 8, 13, 16 6, 7, 14, 15 9, 10 11, 12 Name IN VT VREF_AC nIN VCC VEE Q1, nQ1 nQ0, Q0
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -0.5V to VCC + 0.5 V to the device. These ratings are stress specifi50mA cations only. Functional operation of product at 100mA these conditions or any conditions beyond those 50mA listed in the DC Characteristics or AC Character100mA 0.5mA -65C to 150C 51.5C/W (0 lfpm) istics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT Input Sink/Source, IREF_AC Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current
TO
3.63V; VEE = 0V
Minimum 2.375 Typical 3.3 30 Maximum 3.63 Units V mA
Test Conditions Max., VCC, No Load
TABLE 2B. DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V
Symbol RIN VIH VIL VIN VDIFF_IN IN to VT VREF_AC Output Reference Voltage VCC - 1.525 VCC - 1.4 NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing; NOTE 1 Differential Input Voltage Swing (IN, nIN) (IN, nIN) (IN, nIN) Test Conditions Minimum 40 1.2 0 0.1 0.3 1.28 VCC - 1.325 Typical 50 Maximum 60 VCC VIH - 0.15 1.7 Units V V V V V V
TABLE 2C. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing Conditions Minimum VCC - 1.145 VCC - 1.945 550 1100 800 1600 Typical Maximum VCC - 0.895 VCC - 1.695 Units V V mV mV
NOTE 1: Outputs terminated with 100 across differential output pair.
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
Condition Minimum Typical 2 2.5 350 <15 TBD TBD 20% to 80% 152 Maximum Units GHz GHz ps ps ps fs ps
TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.63V TO -2.375V OR VCC = 2.375 TO 3.63V; VEE = 0V
Symbol fMAX fIN t PD tsk(o) tsk(pp) t jit tR/tF Parameter Output Frequency Input Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time
All parameters characterized at 1GHz unless otherwise noted. RL = 100 after each output pair. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
858012AK
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
VCC
Qx
SCOPE
nIN
LVPECL
VEE
nQx IN
V
IN
Cross Points
V
IH
V
IL
V EE
-0.375V to -1.63V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
nIN IN nQ0, nQ1 Q0, Q1
tPD
OUTPUT SKEW
VIN VIN, VOUT 800mV (typical)
VDIF_IN VDIFF_IN, VDIFF_OUT 1.6V (typical)
PROPAGATION DELAY
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER APPLICATION INFORMATION
LVPECL INPUT
WITH
BUILT-IN 50 TERMINATION INTERFACE (2.5V)
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
2.5V 2.5V
The IN/nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 1A to 1E show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V or 2.5V 2.5V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN 2.5V LVPECL R1 18
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
2.5V 2.5V
FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
2.5V 2.5V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML - Built-in 50 Ohm Pull-up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm R2 25 VT nIN
2.5V
SSTL
Receiver With Built-In 50
FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
858012AK
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V
LVPECL INPUT WITH BUILT-IN 50 TERMINATION INTERFACE (3.3V)
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V 3.3V
Zo = 50 Ohm IN Zo = 50 Ohm LVDS VT nIN
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN LVPECL R1 50
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML- Open Collector
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN CML- Built-in 50 Ohm Pull-Up
Receiver With Built-In 50 Ohm
Receiver With Built-In 50 Ohm
FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH OPEN COLLECTOR
FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
3.3V
3.3V
R1
25
Zo = 50 Ohm IN Zo = 50 Ohm VT nIN
SSTL
R2
25
Receiver With Built-In 50 Ohm
FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
2.5V DIFFERENTIAL INPUT
WITH
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 3.
2.5V 2.5V R1 680 IN VT nIN
R2 680
Receiver with Built-In 50 Ohm
FIGURE 3. UNUSED INPUT HANDLING
3.3V DIFFERENTIAL INPUT
WITH
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 4.
3.3V 3.3V R1 1K IN VT nIN
R2 1K
Receiver with Built-In 50 Ohm
FIGURE 4. UNUSED INPUT HANDLING
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS:
LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50
125
FOUT FIN
125
Zo = 50
Zo = 50 50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FOUT
FIN
Zo = 50 84 84
RTT =
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
ground level. The R3 in Figure 6B can be eliminated and the termination is shown in Figure 6C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 6A and Figure 6B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS858012. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS858012 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.63V * 30mA = 108.9mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.63V, with all outputs switching) = 108.9mW + 60.4mW = 169.3mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 0 linear feet per minute and a multi-layer board, the appropriate value is 51.5C/W per Table 4 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.169W * 51.5C/W = 93.7C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 4. THERMAL RESISTANCE JA FOR 16 LEAD VFQFN, FORCED CONVECTION
JA at 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 51.5C/W
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
3. Calculations and Equations. LVPECL output driver circuit and termination are shown in Figure 7.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.895V
-V
OH_MAX
) = 0.895V =V - 1.695V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.695V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.895V)/50] * 0.895V = 19.78mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.695V)/50] * 1.695V = 10.34mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN
JA at 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
TRANSISTOR COUNT
The transistor count for ICS858012 is: 113 Pin compatible with SY58012U
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 6. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
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REV. A NOVEMBER 28, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858012
LOW SKEW, 1-TO-2, DIFFERENTIAL-TO2.5V, 3.3V LVPECL FANOUT BUFFER
Marking 012A 012A TBD TBD Package 16 Lead VFQFN 16 Lead VFQFN 16 Lead "Lead-Free" VFQFN 16 Lead "Lead-Free" VFQFN Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS858012AK ICS858012AKT ICS858012AKLF ICS858012AKLFT
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark. HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 858012AK
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REV. A NOVEMBER 28, 2005

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